The present invention relates generally to integrated injection logic (I.sup.2 L) and more specifically to an I.sup.2 L structure which is compatible with high voltage bipolar transistors.
I.sup.2 L is a well known bipolar logic form which has high packing density, can be realized in a single isolated island, is operable from a low supply voltage and affords low power dissipation. These characteristics make it attractive as a compatible logic in bipolar linear processes. The fact that it can be built in a single island is particularly attractive in high voltage processes because the isolation methods for high voltage IC's require much area and yield large minimum islands. Thus a single island logic saves much area compared to alternative multiple island approaches.
A well known limitation to the application of I.sup.2 L in high voltage-processes is the large hole storage in the N- portion of the emitter of the inverted NPN which forms the gate of the I.sup.2 L structure. High voltage NPN's require thick, high resistivity N-- collector regions to achieve high BV.sub.CBO and BV.sub.CEO. In addition to the high hole storage in this region of the I.sup.2 L transistor emitter mentioned above which increases propagation delay, the I.sup.2 L NPN emitter efficiency is so lowered that.the gate will not function.
In prior art integrated circuits including I.sup.2 L structure and bipolar transistors, the process step to form the base of the NPN bipolar transistor is used also to form the base of the NPN inverted transistor of the I.sup.2 L. This results in a large N- emitter portion of the I.sup.2 L NPN. Solution to this problem using the aforementioned process is to provide a buried layer of the same conductivity type as the base of the NPN of the I.sup.2 L formed by outdiffusion into the epitaxial layer. This is specifically described in U.S. Pat. No. 4,255,209 to Morcom et al. Since the buried P portion is directly on top of the buried N+ region, the N- emitter region for the inverted NPN of I.sup.2 L has been eliminated. Although this process is satisfactory for low voltage bipolar transistors, as discussed above it is not applicable to high voltage NPN transistors.
Another method of removing the buried N- emitter region is to provide multiple resistivity and multiple buried layers at different depths. An example of the multiple buried layers is described in U.S. Pat. No. 4,087,900 to Yiannoulos. In this patent, an intricate process is used to form the multiple buried layers. The device is structured within the epitaxial layer in the base region of the I.sup.2 L inverted transistor so that the modification of the buried layer is a modification of the buried emitter instead of modification of the base region.
Thus there exists a need for a simple method of fabricating improved I.sup.2 L devices in integrated circuits with high voltage bipolar transistors.